Introduction
Verilog: Your key to digital design
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What you should know
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Setting up your environment
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1. Hardware Description
Hardware description languages
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Digital systems
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Levels of abstraction
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Gate level
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Register-transfer level
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2. Basic Verilog Syntax
Verilog modules
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Instantiating modules
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Gates and primitives
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Registers and wires
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Range specification
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Numbers and constants
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Always blocks
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The if-else statement
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Case statements
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Boolean algebra expressions
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Continuous assignments
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Blocking assignments
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Nonblocking assignments
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Challenge: From schematic to code
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Solution: From schematic to code
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3. Simulation
Simulation basics
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Test bench modules
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Stimulus variables
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Clock generation
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Initial and always blocks
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A simple simulation
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Timing directives
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Display tasks
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Challenge: You run the show
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Solution: You run the show
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4. Combinational Systems
Arithmetic and logic operators
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Challenge: Make a 4-bit arithmetic logic unit (ALU)
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Solution: Make a 4-bit arithmetic logic unit (ALU)
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Getting your ALU on a field-programmable gate array (FPGA)
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A functional demo of the ALU
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5. Sequential Systems
Flip-flops
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Edge sensitivity
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A shift register example
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Challenge: Make a clock divider
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Solution: Make a clock divider
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Getting your clock divider on an FPGA
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A functional demo of the clock divider
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Ex_Files_Learning_Verilog_FPGA_Development.zip
(23.5 MB)